Synopsys Unveils Microsoft Chip Design Tools Cutting Debug Cycle Times by 40%

techsoftware 2 posts · 2 accounts

Synopsys unveiled two autonomous chip-design workflows developed with Microsoft that cut debug cycle times by 25% to 40% in early testing. The platforms automate debug closure and use Azure-based Fusion Compiler to handle implementation and design optimization.

AMD is evaluating the tools for next-generation products, making them the first electronic design automation applications available on Microsoft Discovery. In a separate announcement, the company expanded its partnership with Intel, adding certified flow and packaging support for the 14A node and new high-speed interface intellectual property.

From the sources (2 posts)

@wallstengine

Synopsys $SNPS unveiled two autonomous chip-design workflows with Microsoft $MSFT, with $AMD evaluating them for next-generation products. The first automates debug closure and reduced cycle times by 25% to 40% in early testing. The second

@stocksavvyshay

$SNPS unveils two autonomous chip-design workflows with $MSFT that cut debug cycle times ~40% in early testing with $AMD evaluating them for next-generation products. It also expands support for $INTC 14A and EMIB packaging alongside new h

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