Nvidia Packaging Tests Hit 9.5x Reticle Size Hurdle for Rubin Ultra, Prompting Intel EMIB-T Pitch
A J.P. Morgan seminar notes that Nvidia’s Rubin Ultra processor is encountering significant difficulties in implementation testing for larger reticle sizes on TSMC’s CoWoS-L packaging. Evaluations of a 5.5x reticle are reportedly progressing poorly, while experts consider a 9.5x reticle implementation extremely difficult. A soldering issue has been identified for the 9.5x configuration ahead of 2027, potentially complicating the deployment of Nvidia’s Feynman generation chips in 2029.
The packaging bottlenecks highlight the critical role of advanced chip assembly in next-generation artificial intelligence hardware, raising the stakes for alternative architectures. J.P. Morgan highlighted Intel’s EMIB-T technology as a viable competitor to CoWoS-L. The design utilizes silicon bridges and through-silicon vias to deliver power and signals to memory components, bypassing large interposers to reduce warpage and improve yield, with Intel claiming it can accommodate reticle sizes up to 12x.
From the sources (1 posts)
@jukan05Quoted from a JPM seminar (a must-read): - Rubin Ultra, which is based on a 5.5x reticle size, has encountered difficulties in implementation testing, and the expert believes that a 9.5x implementation will be extremely difficult. As of th