TSMC Develops EMIB-Like Chip Packaging to Compete With Intel and Ease CoWoS Constraints
TSMC is developing a silicon-bridge packaging technology in partnership with substrate maker Kinsus to support larger multi-die artificial intelligence chips, according to The Information. The initiative offers an alternative to its capacity-constrained CoWoS manufacturing line and directly counters Intel’s advanced packaging capabilities.
The project is in its early stages and carries no commercial launch timeline. TSMC is moving to prevent customers such as Nvidia and Google from routing advanced assembly work to Intel, with Nvidia evaluating the rival technology for a future processor and Google having ordered Intel to package more than 3 million custom AI processors for delivery in 2028.
From the sources (7 posts)
@firstsquawkTSMC DEVELOPS AI CHIP PACKAGING TECH TO COUNTER INTEL - INFORMATION
@financialjuiceTSMC develops AI chip packaging tech to counter Intel - The Information $TSM $INTC
@wallstengineTSMC DEVELOPS EMIB-LIKE PACKAGING $TSM is working with substrate maker Kinsus on a silicon-bridge technology designed to support larger multi-die AI chips and provide an alternative to its capacity-constrained CoWoS process. The project re
@jukan05The Information: TSMC Is Developing a New Packaging Technology to Compete With Intel’s EMIB TSMC is wary of Intel. $INTC
@stocksavvyshay$TSM is developing an “EMIB-like” packaging technology to counter $INTC as AI chip designs grow larger and CoWoS capacity remains constrained. The move aims to keep customers like $NVDA and $GOOGL from shifting more advanced packaging work
@polymarketmoneyBREAKING: TSMC develops new AI chip packaging technology to counter Intel.
@firstsquawkTSMC DEVELOPS NEW AI CHIP PACKAGING TECHNOLOGY TO CHALLENGE INTEL