AMD Releases MI500X Instruction Set With Single Shared Tensor Descriptor to Mirror Nvidia Design
aiai-infrastructureai-compute-chips 1 posts · 1 accounts
AMD released the instruction set architecture for its MI500X processor, which incorporates a single tensor data movement descriptor for mixture-of-experts workloads shared across all experts.
The design mirrors a similar capability being added to the MI455X model, referencing the tensor memory architecture from NVIDIA's Hopper generation.
From the sources (1 posts)
@semianalysis_SCOOP – AMD's MI500X ISA JUST GOT RELEASED AND IT HAS 1 TDM MOE DESCRIPTOR SHARED ACROSS ALL EXPERTS. Just like how MI455X is adding TDM (nicknamed RMA), which is a copy of NVIDIA's SM90 Hopper ISA TMA.