TSMC Targets 2029 for CoPoS AI Chip Packaging
TSMC is targeting 2029 for mass production of CoPoS, a panel-level packaging technology designed for AI accelerators, according to DigiTimes. The advanced packaging platform is positioned as the successor to CoWoS, the system currently used to package Nvidia and other high-end AI chips. As AI accelerators continue to increase in physical size, the company aims to transition production from round 12-inch silicon wafers to 310mm by 310mm square panels to overcome a growing manufacturing bottleneck.
The shift addresses efficiency constraints inherent to circular substrates: larger chip designs waste more expensive interposer area at the edges of round wafers. Square panels expand usable area, allowing manufacturers to fit additional compute dies and up to 12 stacks of HBM4 high-bandwidth memory into a single package while lowering packaging costs over time. TSMC has already established a pilot production line for the technology at VisEra’s Longtan plant and is expected to open a second line at AP7 in Chiayi.
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@wallstengineDigiTimes reports TSMC is targeting 2029 for CoPoS, a panel-level AI chip packaging technology that shifts production from round 12-inch wafers to 310mm x 310mm square panels. as AI accelerators get larger, circular wafers waste more expen
@stocksavvyshay$TSM is targeting 2029 for panel-level CoPoS packaging as AI chip scaling shifts from transistor density to packaging capacity. CoPoS could fit more compute dies and up to 12 HBM4 stacks into one package widening TSMC’s moat behind next-ge